The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating an isolation layer in a semiconductor device.
As known, an active region is defined by forming an isolation layer over a substrate using a shallow trench isolation (STI) method.
FIGS. 1A to 1C are cross-sectional views of a method for fabricating a typical isolation layer in a semiconductor device.
Referring to FIG. 1A, a pad oxide layer 102 and a pad nitride layer 103 are formed over a substrate 101 and then patterned to form an isolation layer region. Subsequently, the substrate 101 is etched using the pad oxide layer 102 and the pad nitride layer 103 as an etch barrier to form a trench 104.
A thermal oxide layer 105 is formed in the trench 104. A liner nitride layer 106 and a liner oxide layer 107 are laminated over the resultant surface of the substrate 101 including the trench 104.
Referring to FIG. 1B, a spin on dielectric (SOD) oxide layer 108 is formed to fill a portion of the trench 104 is formed.
Referring to FIG. 1C, a high density plasma (HDP) oxide layer 109 is formed to fill the remaining portion of the trench 104.
The typical method laminates the liner nitride layer 106 and the liner oxide layer 107 over the trench 104 and fills the trench 104 with the SOD oxide layer 108 and the HDP oxide layer 109, thereby forming the isolation layer.
However, a wet etch of the SOD oxide layer is needed to allow the SOD oxide layer 108 to remain in a portion of the trench 104. During the wet etch, the liner oxide layer 107 is damaged and thus the liner nitride layer 106 is exposed on an upper portion of the trench 104. As a result, during a process for forming the HDP oxide layer 109, the liner nitride layer 106 may be damaged by a sputtering, so that a gate oxide integrity (GOI) failure of the semiconductor device may be caused. Consequently, yield and reliability of the semiconductor device is deteriorated.